The present invention relates to analogue to digital converters.
Known interpolating analogue to digital converters usually comprise a relatively coarse resolution analogue to digital (A/D) converter arranged in a feedback loop in combination with a digital to analogue (D/A) converter; the D/A converter having much finer resolution than the coarse A/D converter. The coarse A/D converter is sampled at a high sample rate with subsequent averaging of the output samples obtained from the coarse resolution A/D converter.
The quantised signal appearing at the output of the coarse A/D converter is an approximation of the analogue signal fed to it, the approximation being dependent upon the quantum jump or step size of the quantisation and the sample rate used in the quantisation process. At any point in time, the difference between the analogue input signal and the output sample from the coarse A/D converter is known as the quantisation error; generally termed Q.
The output from the coarse A/D converter is fed to the finer resolution D/A converter, the output of which is fed back and combined with the incoming analogue input signal to be digitised. However the D/A converter utilised also gives rise to errors; generally defined by the resolution of the D/A converter.
Such interpolating A/D converters also include an analogue controller, usually in the form of a high gain amplifier of gain A, in the feed path to the coarse A/D converter.
According to the present invention there is provided an analogue to digital converter comprising combiner means for receiving an analogue input signal, an analogue controller means for receiving an output from the combiner means, a low resolution analogue to digital converter for receiving an output from the analogue controller means, a digital to analogue converter arranged in a feedback loop to the combiner means, the digital to analogue converter comprising an accumulator the output of which is arranged to drive a finite impulse response filter having a plurality of serially coupled delay elements, output signals from which are summed to provide the digital output signal and which serves also to provide the analogue feedback signal which is fed to the combiner means.
In a preferred embodiment the delay elements are one bit delay elements.
In one embodiment the combiner means is a subtractor unit, the analogue input signal being subtractively combined with the analogue feedback signal.
In another embodiment the combiner means is an adder unit, the analogue feedback signal being fed to the combiner means via an inverter and additively combined at the combiner means with the analogue input signal.
Advantageously the digital to analogue converter co mprises a digital overflowing accumulator.